1. Field of the Invention
The present invention relates generally to the field of integrated circuit testing and, more specifically, the present invention relates to a method of making modifications to an integrated circuit.
2. Description of the Related Art
Once a newly designed integrated circuit has been formed on a silicon substrate, the integrated circuit must be thoroughly tested to ensure that the circuit performs as designed. Portions of the integrated circuit that do not function properly must be identified so that they can be fixed by modifying the design the of the integrated circuit. This process of testing an integrated circuit to identify problems with its design is known as debugging. After debugging the integrated circuit and correcting any problems with its design, the final fully functional integrated circuit designs are used to mass produce the integrated circuits in a manufacturing environment for consumer use.
During the debugging process, it is sometimes necessary to add, delete or reroute signal line connections within the integrated circuit. For instance, assume that FIG. 1 shows an integrated circuit 101 that requires edits to be made. In this example, circuit block A 103 is coupled to circuit block B 107 through inverter 105. If it is determined during the debug process that the signal from circuit block A 103 should not be inverted when received by circuit block B 107, integrated circuit 101 may be edited such that inverter 105 is effectively removed from integrated circuit 101 and that circuit block A 103 is directly connected to circuit block B 107.
Using prior art techniques, integrated circuit 101 may be edited as follows. Inverter 105 may be disconnected from circuit block A 103 and circuit block B 107 by physically cutting the signal line as shown in FIG. 1 with cuts 109 and 111. After cuts 109 and 111 are made, circuit block A 103 and circuit block B 107 are no longer connected. In order to reconnect circuit block A 103 and circuit block B 107, passivation is removed from integrated circuit 101 at locations 113 and 115 to expose the buried metal of the signal line connected to circuit block A 103 and circuit block B 107. After the passivation is removed from the signal line at locations 113 and 115, a new metal line 117 is deposited on the integrated circuit substrate over the exposed pieces of metal at locations 113 and 115 to directly connect circuit block A 103 to circuit block B 107.
In general, a focused ion beam (FIB) tool is used to deposit focused ion beam chemical vapor deposition (FIBCVD) lines to edit integrated circuits. The FIB tool is a precision device that can be used to form cuts 109 and 111 and remove passivation from areas such as locations 113 and 115 to form openings in the dielectric areas over the metal lines of an integrated circuit. Since FIB tools are precision devices, FIBCVD lines such as signal line 117 of FIG. 1 may be deposited with high precision to accomplish very complex integrated circuit edits.
A disadvantage with depositing FIBCVD lines with the FIB tool is that the depositing process is very time consuming and results in signal lines having a considerable amount of resistance. Consequently, when very long signal lines need to be deposited during the editing process of an integrated circuit, the resulting signal lines may take a very long time to deposit and may also suffer from an undesirably high amount of resistance.
Another prior art technique used to deposit metal lines is the use of a laser chemical vapor deposition (LCVD) tool. In general, LCVD tools lack the ability to have the same degree of precision as FIB tools. LCVD tools, however, do have the ability to deposit metal lines relatively quickly. In addition, metal lines deposited with LCVD tools are generally low resistance lines in comparison with the metal FIBCVD lines deposited with FIB tools.
FIG. 2 shows an example of one use for an LCVD type tool. In this example, a multi-chip module 201 includes an integrated circuit die 203 and another integrated circuit die 205. In this example, assume multi-chip module 201 must be edited such that bond pad 207 of integrated circuit die 203 must be coupled to bond pad 209 of integrated circuit die 205. An LCVD tool may be used to deposit a metal line 211 between bond pads 207 and 209. Assuming that the distance between bond pads 207 and 209 is relatively long and that the deposition of a signal line between bond pads 207 and 209 does not require an extremely high degree of precision, an LCVD tool is ideally suited to deposit signal line 211. Thus, bond pads 207 and 209 may be coupled to one another in a relatively short period of time with a relatively low resistance signal line 211 by using an LCVD tool.
It is appreciated that there are some instances in which an LCVD tool may be used to perform relatively simple integrated circuit edits. However, it is noted that for edits of integrated circuits that require a great deal of precision, LCVD tools are generally not well suited to perform these complex integrated circuit edits. Moreover, there are LCVD tools that cannot be used practically for removing the passivation over metal lines such as those shown at locations 113 and 115 in FIG. 1. Consequently, in those instances where it is necessary to perform complex edits with long signal lines, FIB tools are generally used to deposit FIBCVD lines in the prior art. Thus, long edited signal lines require a long period time to deposit and also suffer from high resistance.
Therefore, what is desired is a method and an apparatus for editing integrated circuits that has the ability to perform complex edits as well as the ability to deposit long signal lines that have relatively low resistance in a relatively short period of time.